New Cadence SoC Encounter GXL Addresses Customers' Nanometer Design Yield and Variation Challenges; Yield Aware RTL to GDS Implementation Flow Targets Leading-Edge Designs at 65nm and Beyond
SAN JOSE, Calif.—(BUSINESS WIRE)—Dec. 5, 2005—
Cadence Design Systems, Inc. (Nasdaq:CDNS) today
announced the introduction of SoC Encounter(TM) GXL, completing its
Cadence(R) Encounter(R) digital IC design platform product
segmentation strategy. SoC Encounter GXL adds yield as a standard
design target throughout the implementation flow to address both the
'defect' and 'process variation' challenges of advanced designs at 65
nanometers and beyond.
Improving Defect Yields
SoC Encounter GXL addresses nanometer defect yield issues with new
yield analysis and optimization capabilities embedded across the
implementation flow. For yield analysis, a new command, reportYield,
assesses full-chip or block-level defect yield losses based on factors
such as critical area and cell yields. A unique yield prototyping
capability enables users to choose full-chip floorplanning strategies
with visibility of yield considerations before committing to a
physical architecture for the chip.
"Yield analysis and optimization during implementation is critical
for maximizing design yield, especially at 65 nanometers and beyond,"
said Satoshi Andou, general manager, Design Platform Development
Division, Electronic Devices Business Unit of Fujitsu Limited. "With
Encounter GXL, we are now able to analyze and improve yield at any
point in the design flow and evaluate the impact of various design
decisions, without leaving the Encounter platform. Encounter GXL gives
us the confidence that our yield-aware design will correlate to final
silicon."
For yield optimization, SoC Encounter GXL supports cell
optimization in global RTL and physical synthesis using yield-aware
cell libraries in either PDF Solutions' pDFm(TM) or a new Encounter
format. For interconnect optimization, SoC Encounter GXL controls
double via insertion, wire spacing and other factors concurrently
during routing, instead of as a post processing step.
"Yield-aware physical synthesis is one of the highest-impact ways
a design team can address chip yields," said Kevin MacLean, vice
president of DFM at PDF Solutions. "Using SoC Encounter GXL with PDF
Solutions' .pdfm files and pDfx-compliant libraries makes it possible
for designers to easily produce more manufacturable SoC designs
without compromise in other areas like schedule, timing and power."
"The correct choice of library cells can have a significant effect
on production yields at 90 nanometers and below," said Brani Buric,
senior director of platform product marketing and business development
for Virage Logic. "Virage Logic's ASAP Logic Standard Cell Libraries
with yield views will be available for use with SoC Encounter GXL on
the Chartered Semiconductor 90-nanometer process in Q1 2006."
Reducing the Impact of Variation
SoC Encounter GXL incorporates analysis and optimization
capabilities to manage the effects of nanometer process variation on
design performance. This includes a new multimode timing capability to
reduce the complexity of timing optimization in designs with multiple
operating modes, increasingly common in low power and consumer
designs. Cadence plans to add a concurrent multicorner analysis and
optimization function in the first half of 2006, with statistical
timing under development and scheduled for release in the second half
of 2006.
SoC Encounter GXL also reduces overall design variation by
reducing clock variation. Leveraging advanced 'mesh' techniques
traditionally used in high-performance microprocessors, SoC Encounter
GXL automatically synthesizes clock circuits with ultra-low
susceptibility to process variation. On a high-performance
communications design taped out in October 2005, an SoC Encounter GXL
clock mesh provided an estimated 50 percent reduction in overall
on-chip timing variation.
"Below 130 nanometers, precision clock design is critical to
control hold time and skew variation over process, and across the
entire design simultaneously," said Kun-Cheng Wu, Director of Design
Development at Faraday Technology. "We are pleased with SoC Encounter
GXL's clock mesh synthesis. With it, we have been able to quickly
produce low-skew, low-variation clock structures which reach
aggressive constraints."
"Controlling defect- and variation-related yields is a top
consideration of designers ramping to advanced process technologies,"
said Wei-Jin Dai, corporate vice president, R&D for Cadence. "High-end
development teams now expect the design phase to help solve this
problem; not only through EDA analysis and optimization, but also
through new circuit-design techniques and closer integration with
manufacturing. With SoC Encounter GXL, we deliver this in an easily
adoptable form to facilitate the next generation of SoC complexity and
help put the Design in design-for-yield. In 1H06, we plan to introduce
new DFM technology developed under Cadence's 'Catena' incubation
project that will continue to meet these challenges."
"As time-to-market windows continue to shrink along with process
geometries, the emphasis on making informed design choices to speed
yield ramp intensifies," said Walter Ng, senior director of platform
alliances at Chartered Semiconductor Manufacturing. "Bringing
critical, calibrated manufacturing information into design requires
close collaboration between semiconductor, IP and EDA companies.
Chartered and Cadence are actively driving solutions, including SoC
Encounter GXL, to help address those challenges facing leading-edge
SoC designers."
Cadence product segmentation strategy, announced at CDNLive! in
September, provides customers with multiple levels of technology
tailored to specific levels of design complexity. Cadence design
platforms now offer a tiered range of products scaled to different
complexities of digital IC design.
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, printed circuit boards and systems used in consumer
electronics, networking and telecommunications equipment, and computer
systems. Cadence reported 2004 revenues of approximately $1.2 billion,
and has approximately 5,000 employees. The company is headquartered in
San Jose, Calif., with sales offices, design centers, and research
facilities around the world to serve the global electronics industry.
More information about the company, its products, and services is
available at www.cadence.com.
Cadence, Encounter and the Cadence logo are registered trademarks
and SoC Encounter is a trademark of Cadence Design Systems, Inc. All
other trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302
Email Contact
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